In high speed data communications between integrated circuits (systems), it often occurs that the signals transmitted from one integrated circuit to another one cannot be reliably sampled on a predetermined clock signal. In this case, it is common to over sample the data signal by using the different phases of a reference clock signal generated by a multiphase clock oscillator. Then, a data recovery circuit is used to determine which of the sampled signals is the best one and must be kept to represent the recovered data for subsequent processing. Such a sampling technique is extensively used in case of high speed asynchronous serial binary data communications where the clock signal is not transmitted to the receiving device. It can also be used in case of multiple data signals transmitted in parallel when the difference in data paths results in a difference in arrival times at the receiving device. Unfortunately, over sampled data signals come out as multiple signals, each one being related to a particular phase of the multiple phase clock signal. In order to reliably transmit the recovered data signal for further processing, it is necessary to realign the selected sampled signal relative to a predefined phase of the multiphase clock signal. This major problem has received a number of solutions so far, such as described in the prior art following references.
For instance, U.S. Pat. No. 6,026,134 covers some data recovery issues using an over sampling technique but does not teach how the over sampled data signal may be realigned on a predefined phase of the multiphase clock signal.
U.S. Pat. Nos. 5,487,095 and 5,550,860 describe circuits consisting of an array of resistors or delay elements to detect data edges and select the sample to recover. However, delay elements and resistors are known to be highly dependent on manufacturing process variations. In addition, there is a significant signal jitter induced by power supply variations. As a consequence, these circuits are therefore inadequate for high speed serial binary data communication applications. Moreover, the section that selects the best sampled signal for each bit of the incoming data implies a combinatory logic to demultiplex the selected sampled signal which may cause additional delay or data skew problems in such high speed applications due to the existence of different paths. Finally, these circuits are relatively complex, consuming thereby much silicon area and are not adequate for LSSD (Level Sensitive Scan Design) which allows excellent testability.